1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a multi-channel semiconductor integrated circuit for driving a capacitive load, such as particularly a plasma display or the like.
2. Description of the Related Art
As a conventional high-withstand voltage driver circuit, there is a known half-bridge circuit including a P-channel MOS transistor and an N-channel MOS transistor (see, for example, FIG. 5 in Japanese Unexamined Patent Application Publication No. 2006-94301).
FIG. 6 is a diagram showing a circuit configuration of a conventional drive circuit which is often used as a scanning driver circuit for plasma display panel (PDP) apparatuses.
In FIG. 6, a high-withstand voltage driver 19 comprises a high-withstand voltage output 10 including a high-side transistor 11 and a low-side transistor 12, and a level shift circuit 9 for driving the high-side transistor 11. Note that 8 indicates a pre-driver for driving the level shift circuit 9 and the low-side transistor 12, 4 indicates a high-withstand voltage output terminal, 3 indicates a high-voltage power supply terminal for 100 V or more (VDDH), and 2 indicates a low-voltage power supply terminal for about 5 V (VDD).
Hereinafter, an operation of the high-withstand voltage driver 19 of FIG. 6 will be described with reference to FIG. 7.
FIG. 7 is a timing diagram for describing the operation of the conventional high-withstand voltage driver 19.
FIG. 7 shows input signals IN and HIZ which are input from a low-withstand voltage control section to control signal input terminals 5 and 6, output signals IN1 and IN2 of the pre-driver 8 which are used to drive the level shift circuit 9 in accordance with the input signals IN and HIZ, an output signal IN3 of the pre-driver 8 which is used to drive the low-side transistor 12 in accordance with the input signals IN and HIZ, an output signal IN4 of the level shift circuit 9 which is used to drive the high-side transistor 11 in accordance with the output signals IN1 and IN2 of the pre-driver 8, and a voltage waveform OUT of the high-withstand voltage output terminal 4 which is output in accordance with the output signal IN3 of the pre-driver 8.
Firstly, a case where the input signal HIZ of the control signal input terminal 6 is at the H level (VDD) will be described.
In this case, an AND circuit 31 is in a state in which its output will be determined, depending on the input signal IN of the control signal input terminal 5. In this state, when a signal having the GND level is input to the control signal input terminal 5, i.e., the input signal IN goes to the L level (GND), the output of the AND circuit 31 goes to the L level, the output signal IN1 of an inverter 32 goes to the H level (VDD), and the output signal IN2 goes to the L level (GND). As a result, in the level shift circuit 9, an N-channel MOS transistor 15 is switched ON, a P-channel MOS transistor 14 is switched ON, an N-channel MOS transistor 16 is switched OFF, and a P-channel MOS transistor 13 is switched OFF, so that the output signal IN4 goes to the H level (VDDH). As a result, the high-side transistor 11 is switched OFF, and the output signal IN3 of an AND circuit 33 goes to the H level (VDD), so that the low-side transistor 12 is switched ON, and therefore, the high-withstand voltage output terminal 4 goes to the L level (GND).
Conversely, it is assumed that a signal having the VDD level is input to the control signal input terminal 5, i.e., the input signal IN goes to the H level (VDD). In this case, in the level shift circuit 9, the N-channel MOS transistor 15 is switched OFF, the P-channel MOS transistor 14 is switched OFF, the N-channel MOS transistor 16 is switched ON, and the P-channel MOS transistor 13 is switched ON, so that the output signal IN4 goes to the L level (GND), the high-side transistor 13 is switched ON, and the output signal IN3 goes to the L level (GND). As a result, the low-side transistor 14 is switched OFF, so that the high-withstand voltage output terminal 4 goes to the H level (VDDH).
Next, a case where the input signal HIZ of the control signal input terminal 6 is at the L level (GND) will be described.
In this case, the outputs of the AND circuits 31 and 33 go to the L level (GND) and the output of the inverter 32 goes to the H level. As a result, the high-side transistor 11 is switched OFF and the low-side transistor 12 is also switched OFF, so that the high-withstand voltage output terminal goes to the high-impedance state.
The conventional high-withstand voltage driver in multi-channel semiconductor integrated circuits has a problem that, when the high-withstand voltage output terminal is short-circuited due to any external factor, the device may be broken, depending on the current overload capacity and short-circuit time of the device.
There is also a problem that, when a short-circuit protection circuit which is used in a typical low-withstand voltage circuit is applied to a high-withstand voltage multi-channel driver circuit, the chip area increases.